電氣電子工程paper
12-06, 2012
HDL FOR PROGRAMMABLE LOGIC WITH PROJECT
MODULE CODE: H64HPP
Project – ADC Controller Core Design
1 INTRODUCTION
兩個最廣泛部署的圖像傳感器技術CCD（電荷耦合器件）和CMOS（互補金屬氧化物半導體）。這是眾所周知的，CCD相機提供更高的圖像質量，但苦于較低的讀出速度。相反，較目前的CMOS攝像頭，CCD攝像頭，技術稍微降低圖像質量。
The two most widely deployed image sensor technologies are CCD (charge coupled device) and
CMOS (complementary metal oxide semiconductor). It is www.400190.com/media well known that the CCD camera offers
higher image quality, but suffers from lower read-out speed. On the contrary, compared with the
CCD camera, the current CMOS camera technology has slightly lower image quality. However, the
CMOS camera enjoys high-speed random access to the image pixels of interest which means that
data can be rapidly transferred to a digital signal processor.
One of the research projects we are investigating is full-field laser Doppler blood flowmetry, in
which an in-house designed CMOS camera route has been followed. Such an approach offers highspeed
random access to individual pixels.
Aout0
CMOS CAMERA
(32x32 pixels)
Aout1
Aout2
Aout31
C0
5-to-32 Decoder
32-to-1 Multiplexer
ADS5545 based
ADC Module
Ain ADC Controller
Core
CLKIN
CLKOUT
D
SCLK
SEN
SDATA
14
5 5
ROW
COL
C1
C2
C31
Reset
Clock40M
DataReady
ReadData
ReadAddress
ReadEnable
14
10
Xilinx Spartan-3E FPGA
(XC3S500E-FG320-5 )
Start
ReadClock
32×32的全域激光多普勒血流儀監測的數據采集系統.我們已經開發了一個滿場的研究大小為32x32像素的CMOS攝像頭芯片
激光多普勒血流儀監測..
Fig.1 The data acquisition system for the 32x32 full field laser Doppler blood flowmetry
We have developed a CMOS camera chip of size of 32x32 pixels for the research of full-field
laser Doppler blood flowmetry. In this chip, in order to reduce the number of analogue outputs, 32
analogue outputs rather than 1024 analogue outputs are adopted, in which 32 pixels share one#p#分頁標題#e#
analogue output. Conventional laser Doppler systems usually require a sampling frequency of at
- 2 -
least 40KHz for each pixel, and hence a sample rate of 40MSPS (Mega Samples Per Second) is
required for the CMOS camera chip of 32x32 pixels if a single ADC channel is used. In addition,
the low modulation depths (~1%) of laser Doppler blood flow signals means that a high number of
bits are usually required. Therefore, a single channel ADC module with high-speed (1-170MSPS)
and high-resolution (14 bits) has been developed based on TI ADS5545 [1]. The entire prototyping
system as shown in Fig.1, consists mainly of the 32x32 pixel CMOS camera chip, a single channel
ADS5545 based ADC module and Xilinx Spartan-3E FPGA device (XC3S500E-FG320-5 [2]),
which is not only used to implement required real-time data-processing algorithm (e.g. FFT
processing), but also used as a microcontroller to control both the CMOS camera chip and the ADC
module.
2 PROJECT DESCRIPTION
您可以聯系本站QQ: 923678151,咨詢熱線電話:13917206902
You are asked to develop (write, simulate) an ADC controller core as shown in Fig.1 and
implement the core on Xilinx Spartan-3E FPGA device, XC3S500E-FG320-5 [2]. In this ADC
controller core, the following two key functions must be implemented.
ADC sampling: It can be seen from Fig.1 that the ADC controller core sends the address signals,
ROW (5 bits) and COL (5 bits) to enable a particular pixel to be sampled by the ADC module
through a digital 5-to-32 decoder and an analogue 32-to-1 multiplexer. For example, if signals,
ROW and COL, are “01111” and “10101”, respectively, the pixel at the 15th row and 21st column
is going to be routed to the analogue input of the ADC module. On the other hand, it can also be
known from Fig.2, which is taken from the Figure 1 in the ADS5545 datasheet [1] that there is a
sampling latency of 14 cycles. In the ADS5545 based ADC module, the differential clock (Input
Clock as shown in the Figure 1 in the ADS5545 datasheet) is generated from the single-end clock,
CLKIN, via a RF transformer. In terms of CLKIN, the ADC sampling happens at the rising edge of
CLKIN rather than at the falling edge of CLKIN. Furthermore, you must use CLKOUT to clock out
the digital sampled data since the rising edge of CLKOUT perfectly matches the digital sampled
data.
Fig.2 Timing diagram for ADS5545 sampling
如果您有論文代寫需求，可以通過下面的方式聯系我們
點擊聯系客服